The present disclosure relates to processor cores, and more specifically, to the architecture and use of physical register files in processor cores having multiple execution slices.
In modern computer architecture, there are several known ways to design a single computer adapted to perform more than one instruction at a time, or at least in the same time frame. For example, such a computer may include more than one processor core (i.e., central processing unit) and each processor core may be capable of acting independently of other processor cores. This may allow for true multitasking, with each processor core processing a different instruction stream in parallel with the other processor cores of the computer. Another design to improve throughput may be to include multiple hardware threads within each processor core, with the threads sharing certain resources of the processor core. This may allow each processor core to take advantage of thread-level parallelism.